1. Field of the Invention
The present invention relates to a method of manufacturing dummy patterns. More particularly, the present invention relates to a method of forming dummy patterns and spacers of a gate structure, simultaneously.
2. Description of the Related Art
Planarization is very important in ULSI technology. It can provide a smooth surface to ensure good metal step coverage and to provide a flat-enough field so that, within the lithography depth of focus, contact vias and metal wires can be patterned.
A true global planarization can be achieved by chemical/mechanical polishing (CMP) of an inter-layer dielectric (ILD). FIGS. 1A to 1E show cross-sectional views of the conventional processes of CMP. Referring to FIG. 1A, polysilicon patterns 102a, 102b, and 102c are formed on the substrate 100. As shown in FIG. 1A, the poly patterns 102a, 102b, 102c are densely arranged in region 101a, in what is called a dense region. In contrast, the region 101b is an open area called sparse region.
Referring to FIG. 1B, an oxide layer 104 is formed on the substrate 100 and covers the poly patterns 102a, 102b, and 102c.
Referring to FIG. 1C, the oxide layer 104 is etched back to form spacers 104a, 104b, and 104c.
Referring to FIG. 1D, an ILD layer 106 is blanket-formed over the entire surface of substrate 100, which surface includes both the dense region 101a and the sparse region 101b. As shown in FIG. 1D, the poly patterns cause a rough topography on the surface of ILD layer 106.
Referring to FIG. 1E, the surface topography of the ILD layer 106 caused by previously formed polysilicon can be smoothed by polishing the ILD layer 106 with CMP.
However, the dense region 101a and sparse region 101b have different device densities. Therefore, as shown as FIG. 1E, the two regions have different polishing rates. As a result, a dishing effect occurs and reduces the resolution of lithography.